second generation decoder



This page describes a new decoder for HRPT and derived formats. It is also suitable for future developments.


Free software is available for capturing and some simple processing, both for Linux and Windows.

Stored data format is supported by HRPTReader.

Important notes


The hardware contains 3 main parts (see photo) The 3-digit display at the bottom is optional. It shows the state of the decoder: Most important monitor info is also available on pins, where it can be used to drive LED's.

  • Note: The (green) jumper just above the dip-switches sets the needed VCO frequency to 21.2 MHz. Without this jumper 10.6 MHz is needed. Preferred (and for newest firmware) 21.2 MHz is needed!

    Using a VCXO instead of VCO

    A much better result can be achieved using a VCXO instead of a VCO with 74HC04. For more info see:
  • in Dutch: KM2018_3.pdf, page 9
  • In English: KM2018_3.pdf, page 11

    List of components

    To program the FPGA a download cable is needed:


    GODIL has following power-pins:

    All power-pins are connected to each other on the GODIL module, all GND-pins are connected to each other. Normally there is no need to connect each and every pin. I think if you take the ones at the corners that's enough:

    For C and L around VCO several values can be used: For 10.6 MHz:

    For 21.2 MHz (preferred!)
    Note about USB modules: This is FTD245 based. Tested are:


    NOTE: Inserting a jumper means: Set to 0!
  • x : jumper set
  • - : jumper not set
  • * : don't care
  • 1 : logical '1', +5 V
  • 0 : logical '0', 0 V

    Choice decoder/generator type.

    There are currently 4 decoder/generator types implemented; HRPT, CHRPT, MHRPT and FY3A/B + FY3C
    NOAA20 and Aqua are under beta / under construction.
    The type can be set in 2 ways: by software or using jumpers.
    Next table shows jumper setting (left half) and logic value (right half).
    GODIL PinC25A24C23A22C25A24C23A22comment
    Type J1J2J3J4valvalvalval
    HRPT xxxx0000
    CHRPT -xxx1000not active
    MHRPT1 x-xx0100not active
    MHRPT2 --xx1100
    METOP xx-x0010
    FY3A,B x--x0110
    FY3C -x-x1010
    IQ record---x1110
    set by SW***-***1


    You can choose between 3 different VCO frequencies. A higher frequency may give better results with integrator On.

    LC oscillator Firmware versions 05 and older.

    Recommended (mandatory for 2017 firmware loads): 21.292 MHz. (Note: You need to adapt L and C too for a different frequency.)
    Pin C17A16C17A16
    Freq MHz J9 J10valval Note
    10.646 MHzx x 0 0 don't use for 2017+ firmware!
    21.292 MHz- x 1 0 Use this for any firmware
    42.584 MHzx - 0 1 Use this for any firmware
    10.646 MHz- - 1 1 don't use for 2017+ firmware!

    VCXO (recommended) Firmware versions 07 and higher.

    Pin C17A16C17A16
    Freq MHz J9 J10valval Note
    ---x x 0 0 don't use!
    20.000 MHz- x 1 0 May be used for any firmare
    40.000 MHzx - 0 1 May be used for any firmare
    ---- - 1 1 don't use!

    Other settings.

    function Pinjumpersetval
    enable integrator C21J5 - 1
    disable integratorC21J5 x 0
    invert input A20J6 x 0
    normal input A20J6 - 1
    middle display: quality input sig C19J7x0
    middle display: lock state PLL C19J7-1
    If no jumpers are set then all inputs are '1', so:

    Extra monitor points

    data clockB24These are EXOR-ed to phd
    VCO clockB22
    datachange eyecenterB20pulse width=1 VCO clockcycle
    out-syncD25lockindication 2-colour-LED
    1=VCO too highD21VCO lock indication
    1=VCO too lowD19
    1=buffer overflowD11

    Signals on ABCD connectors

    K4: right conGODIL conFPGA conname-left con/dipswGODIL conFPGA conname
    1D1P91Generator out (I) C1P26usb_data[0]
    2B2P12Generator out (Q) A2P15usb_data[1]
    3D3P11decoder in (I) C3P16usb_data[2]
    4B4P10decoder in (Q) A4P95usb_data[3]
    5D5P9scl C5P18usb_data[4]
    6B6P90diseqc_do[0] A6P17usb_data[5]
    7D7P5sda C7P94usb_data[6]
    8B8P4diseqc_do[1] A8P22usb_data[7]
    9D9P2TX RS232 C9P23usb_rd
    10B10P3- A10P33usb_wr
    11D11P98ovf C11P32usb_txe
    12B12P92- A12P34usb_rxf
    13D13P88clkb: VCO C13P38-
    14B14P85sd_sample[0] A14P40-
    15D15P79phd C15P41-
    16B16P78sd_sample[1] A16P36sel_vco[1]
    17D17P83clka: VCO C17P35sel_vco[0]
    18B18P84- D8A18P53sel_clk
    19D19P86ool[0] D7C19P54dispmode
    20B20P71errpls D6A20P57dinv_not
    21D21P70ool[1] D5C21P58ena_bitintegr
    22B22P68ckvco D4A22P60dectype sw/manual
    23D23P67rg_syncled[0] D3C23P61dectype[2]
    24B24P66ckdat D2A24P62dectype[1]
    25D25P65rg_syncled[1] D1C25P63dectype[0]

    Signals on display connector

    GODIL conFPGA conname

    Not on any connector

    FPGA conname

    Programming the FPGA.

    You need the already mentioned program cable and Impact software, free to download from the Xilinx web-page.

    Download and install Impact software.

    There are versions for Linux and Windows. Easiest is to download Impact from an older version of ISE. Go to:
  • Xilinx download web-site
  • Choose ISE Design Tools
  • Choose Archive (left list)
  • Choose 12.2
  • Scroll down to chapter 'Lab Tools'
  • Select 'All Platforms'.
    Now you need to log in, or first make an account. If you have done that, you can download:
  • In Archive tool, which should pop-up now, select xsetup (Linux) of xsetup.exe (Windows)

    (To continue)

    After downloading and installing you should now have a tool called impact(.exe), located at: (location may differ)

    Program the FPGA using Impact.

    There are 2 methods:
    1. Use the gui
    2. Use the command file, and a command shell
    Although it is probably not what you are used to, using the command shell and command file is by far much easier than using the gui!

    Instead of programming the flash you can also program directly into the FPGA. The flash is then not changed; after a power-cycle the original program in flash is loaded. In this way it possible to try a new program before "definitely" load it into flash.

    Bit files and command files are available here.



    The same mcs and cmd may be used. Command: (adapt command filename if needed)
  • impact -batch impact_flsh.cmd Or:
  • impact -batch impact_fpga.cmd

    FPGA loader

    This loader enables a simple selection and loading of firmware for the decoder. The firmware loader contains FPGA firmware for several releases of the HRPT etc. decoder. Loading the firmware needs following steps: For Linux, if you have a search path to 'impact' (the actual Xilinx loader) then this should just work.

    For Windows, if no search path is defined to 'impact', an option can be added to define full path to the impact tool. This needs to be defined in the startup-icon, at 'property', e.g.:
    ld_fpga C:\Xilinx\labtools\ISE\impact.exe

    Newest load contains:

    Decoder details (version 2023)

    framesatelliteinput speedcodingoutput speedstatus
    HRPTNOAA19, 18 etc.1.3308 Mb/sManchester0.6654 Mb/sOK
    AHRPTNOAA202x 15 Mb/sViterbi 1/215 Mb/snot tested with real data yet
    generator gives METOP-like data
    AHRPTNOAA212x 25 Mb/sViterbi 1/225 Mb/snot tested with real data yet
    generator gives METOP-like data
    AHRPTMeteor MN2 *1.3308 Mb/sManchester0.6654 Mb/sOK
    AHRPTMETOP2x 2.333 Mb/sViterbi 3/43.5 Mb/sOK
    AHRPTFY3AB2x 2.8 Mb/sViterbi 3/44.2 Mb/sOK
    AHRPT?Aqua2x 7.5 Mb/snone15 Mb/snot tested with real data yet
    generator gives METOP-like data
    needs half bit shift on Q to do SQPSK

    Differences between versions:

    Some possible advantages/disadvantages:

    Version 10, 2022.01:

    VersionsDateContentclockloader Linuxloader Windows
    01 2017.8 decoders, generators, DiSEqC (needs trimming of vco between sat-types) VCO ~ 21.29 MHz ldfpga_1578a.tgz setup_ldfpga_1578a.exe
    05 2017.8 decoders, generators, DiSEqC; more accurate deriving base clock VCO 21.00 MHz
    07 2018.2 decoders, generators, DiSEqC; very accurate deriving base clock VCO / VCXO 20.000000, 40.000000, 80.000000 MHz
    08 2018.8 better metop/fengyun generator (gives test pictures)
    higher display update rate
    VCO / VCXO 20.000000, 40.000000, 80.000000 MHz
    10 2022.01 Added NOAA20 decoder/generator
    (generator currently generates metop@noaa20 rate)
    Added Aqua decoder/generator
    (generator currently generates metop@noaa20 rate)
    Added UART connection (38.4 kb/s) to use with receiver, to enable frequency set from PC
    VCO / VCXO 20.000000, 40.000000, 120.000000 MHz
    11 2023.07 Added NOAA21 decoder/generator
    (generator currently generates metop@noaa21 rate)
    Corrected Aqua: OQPSK, IQ-rotate if out-sync
    show syncstate aqua on LED display
    VCXO 20.000000, 40.000000, 120.000000 MHz ldfpga_11072023.tgz
    12 2024.01 Added NOAA21 decoder/generator
    (generator currently generates metop@noaa21 rate); OLED
    OLED display driver
    VCXO 20.000000, 40.000000, 120.000000 MHz ldfpga64.tgz

    Older releases

    Bitfiles for XC500 on GODIL 50 board. Contains:
    VersionContentBit-fileCommand fileComment
    V2_1 (2015.01) Flash load nfm_hrptdecgen_2015_01.mcs impact_flsh_2015_01.cmd To load into flash
    V2_1 (2015.01) direct load nfm_hrptdecgen_2015_01.bit impact_fpga_2015_01.cmd To load into FPGA directly, needs to be done each time after power-up (flash content not changed)

    Bitfiles including METOP and Fengyun decoders.

    This load contains:
    VersionContentBit-fileCommand fileComment
    V0_1 (2017.04) Flash load hcmMFdecgen_flsh_01042017.mcs impact_hcmMFdecgen_flsh_01042017.cmd To load into flash
    V0_1 (2017.04) direct load hcmMFdecgen_fpga_01042017.bit impact_hcmMFdecgen_fpga_01042017.cmd To load into FPGA directly, needs to be done each time after power-up (flash content not changed)

    Extra command file for Windows

  • program2flash.bat (program to flash)
  • program2fpga.bat (program into FPGA; program lost after power-cycle)
    nfm_hrptdecgen_2015_01.xcf: pinning of the FPGA. Not needed, just for your information. (This file was used for pinning during generation of the bit-file.)

    release info:

  • V0_1 2017.04: added METOP, Fengyun; use 20 MHz for VCO!
  • V2_0: added Meteor-HRPT (N1, N2) and LRIT
    Added DiSEqC driver for 2 rotors
  • V1_0: Same as V0_7, but now officially released
  • V0_7: select VCO freq.: 10, 20, 40 MHz
  • V0_5: CHRPT generator output: bit-rate now really 1/2 of HRPT

    Older versions

    V1_0 (2011.03) Flash load nfm_hrptdecgen.mcs To load into flash
    direct load nfm_hrptdecgen.bit To load into FPGA directly, needs to be done each time after power-up

    pinning nfm_hrptdecgen_v10.xcf

    V0_7 (2011.03) direct load nfm_hrptdecgen_v07.bit To load into FPGA directly, needs to be done each time after power-up
    Flash load nfm_hrptdecgen_v07.mcs To load into flash
    V0_5 (2011.02) direct load nfm_hrptdecgen_v05.bit To load into FPGA directly, needs to be done each time after power-up
    Flash load nfm_hrptdecgen_v05.mcs To load into flash
    pinning nfm_hrptdecgen_v05.xcf

    Capture software

    See wsat for Windows
    Or wsat for Linux

    Information on using ISE/IMPACT

    More detailed information about how to synthesize vhdl and to make a bit-file can be found here: ISE (including Impact) information

    Received pictures

    The decoder is already build several times. For some example results see: received HRPT pictures

    Extra outputs.

    To control receiver and antenna rotors several outputs are available: