New generation decoder

Content


Introduction.

This page describes a new decoder for HRPT and derived formats. It is also suitable for future developments.

Features:

Free software is available for capturing and some simple processing, both for Linux and Windows.

Stored data format is supported by HRPTReader.


Important notes


Hardware.

The hardware contains 3 main parts (see photo) The 3-digit display at the bottom is optional. It shows the state of the decoder: Most important monitor info is also available on pins, where it can be used to drive LED's.

  • Note: The (green) jumper just above the dip-switches sets the needed VCO frequency to 21.2 MHz. Without this jumper 10.6 MHz is needed.

    List of components

    To program the FPGA a download cable is needed:

    Schematic

    GODIL has following power-pins:

    All power-pins are connected to each other on the GODIL module, all GND-pins are connected to each other. Normally there is no need to connect each and every pin. I think if you take the ones at the corners that's enough:

    For C and L around VCO several values can be used: For 10.6 MHz:

    For 21.2 MHz:
    Note about USB modules: This is FTD245 based. Tested are:

    Jumpers

    NOTE: Inserting a jumper means: Set to 0!
  • x : jumper set
  • - : jumper not set
  • * : don't care
  • 1 : logical '1', +5 V
  • 0 : logical '0', 0 V

    Choice decoder/generator type.

    There are currently 3 decoder/generator types implemented; HRPT, CHRPT and MHRPT.
    Two more are under beta / under construction: LRIT MSG/GOES and FY3.
    The type can be set in 2 ways: by software or using jumpers.
    Next table shows jumper setting (left half) and logic value (right half).
    GODIL PinC25A24C23A22C25A24C23A22comment
    Type J1J2J3J4valvalvalval
    HRPT xxxx0000
    CHRPT -xxx1000
    MHRPT x-xx0100
    LRIT --xx1100prelim.
    FY3 xx-x0010prelim.
    HRPT ---x1110and rest of J1-J3 combinations
    set by SW***-***1
    Note: Corrected 25-5-2014; manual codes CHRPT/MHRPT were swapped. (HW NOT changed!)

    VCO

    You can choose between 3 different VCO frequencies. A higher frequency may give better results with integrator On. Recommended: 21.292 MHz. (Note: You need to adapt L and C too for a different frequency.)
    Pin C17A16C17A16
    Freq MHz J9 J10valval
    10.646 MHzx x 0 0
    21.292 MHz- x 1 0
    42.584 MHzx - 0 1
    10.646 MHz- - 1 1

    Other settings.

    function Pinjumpersetval
    enable integrator C21J5 - 1
    disable integratorC21J5 x 0
    invert input A20J6 x 0
    normal input A20J6 - 1
    middle display: quality input sig C19J7x0
    middle display: lock state PLL C19J7-1
    If no jumpers are set then all inputs are '1', so:

    Extra monitor points

    functionpincomment
    data clockB24These are EXOR-ed to phd
    VCO clockB22
    datachange eyecenterB20pulse width=1 VCO clockcycle
    out-syncD25lockindication 2-colour-LED
    in-syncD23
    1=VCO too highD21VCO lock indication
    1=VCO too lowD19
    1=buffer overflowD11

    Display info

    The 7-segment display is a bit limited in showing non-numeric characters.

    Display 1
    Modein-syncout-syncNote
    HRPTHh
    CHRPTCc
    MRPTΠπreal M not possible with 7-segment display

    Display 2; J7 open: lock state, integrator
    displmeaningcomment
    I Integrator on
    _ VCO out-of-sync; frequency too lowbottom segment(d)
    ¬ VCO out-of-sync; frequency too hightop-segment(a)

    Display 3; J7 open: data-buffer
    displmeaningcomment
    SStopped (S "looks like" 5)
    (empty)=filled between 0% and 25%
    _filled between 25 and 50%bottom segment(d)
    -filled between 50 and 75%middle segment(g)
    ¬filled between 75 and 100%top segment(a)
    FFull

    Display 2,3; J7 set: Quality signal
    displmeaningcomment
    00FFperfect qualityhigher value= lower quality;
    decoder must be in-sync


    Signals on connectors

    K4: right conGODIL conFPGA conname
    1D1P91Generator out (I)
    2B2P12Generator out (Q)
    3D3P11decoder in (I)
    4B4P10decoder in (Q)
    5D5P9scl
    6B6P90diseqc_do[0]
    7D7P5sda
    8B8P4diseqc_do[1]
    9D9P2-
    10B10P3-
    11D11P98ovf
    12B12P92-
    13D13P88-
    14B14P85-
    15D15P79phd
    16B16P78-
    17D17P83clk VCO
    18B18P84-
    19D19P86ool[0]
    20B20P71errpls
    21D21P70ook[1]
    22B22P68ckvco
    23D23P67rg_syncled[0]
    24B24P66ckdat
    25D25P65rg_syncled[1]

    Programming the FPGA.

    You need the already mentioned program cable and Impact software, free to download from the Xilinx web-page.

    Download and install Impact software.

    There are versions for Linux and Windows. Easiest is to download Impact from an older version of ISE. Go to:
  • Xilinx download web-site
  • Choose ISE Design Tools
  • Choose Archive (left list)
  • Choose 12.2
  • Scroll down to chapter 'Lab Tools'
  • Select 'All Platforms'.
    Now you need to log in, or first make an account. If you have done that, you can download:
    Xilinx_LabTools_12.2_.63c.1.1.tar
  • In Archive tool, which should pop-up now, select xsetup (Linux) of xsetup.exe (Windows)

    (To continue)

    After downloading and installing you should now have a tool called impact(.exe), located at: (location may differ)


    Program the FPGA using Impact.

    There are 2 methods:
    1. Use the gui
    2. Use the command file, and a command shell
    Although it is probably not what you are used to, using the command shell and command file is by far much easier than using the gui!

    Instead of programming the flash you can also program directly into the FPGA. The flash is then not changed; after a power-cycle the original program in flash is loaded. In this way it possible to try a new program before "definitely" load it into flash.

    Bit files and command files are available here.

    Windows:

    Linux:

    The same mcs and cmd may be used. Command: (adapt command filename if needed)
  • impact -batch impact_flsh.cmd Or:
  • impact -batch impact_fpga.cmd


    FPGA loader

    This loader enables a simple selection and loading of firmware for the decoder. The firmware loader contains FPGA firmware for several releases of the HRPT etc. decoder. Loading the firmware needs following steps:

    For Linux, if you have a search path to 'impact' (the actual Xilinx loader) then this should just work.

    For Windows, if no search path is defined to 'impact', an option can be added to define full path to the impact tool. This needs to be defined in the startup-icon, at 'property', e.g.:
    ld_fpga C:\Xilinx\labtools\ISE\impact.exe

    This load contains:

    Load 5 uses Digital Clock Managers. These are frequency synthesizers, used in combination with dividers to set the central VCO frequency as close as possible to the received data rate. No trimming of VCO is needed if switching between e.g. HRPT and Fengyun.

    Load 1 doesn't contain DCM's thus needs VCO trimming.

    As far as we can see the DCM's don't degrade decoding quality, so load 5 would be the preferred version to use. (DCM's have restrictions on jitter at the input frequency).
    VersionsContentloader Linuxloader Windows
    2017.8 01 decoders, generators, DiSEqC (no DCM's used; needs trimming of vco) ldfpga.tgz setup_ldfpga.exe
    2017.8 05 decoders, generators, DiSEqC; beta; 2 dcm's (no trimming needed of VCO when switching between satellite types)


    Older releases

    Bitfiles for XC500 on GODIL 50 board. Contains:
    VersionContentBit-fileCommand fileComment
    V2_1 (2015.01) Flash load nfm_hrptdecgen_2015_01.mcs impact_flsh_2015_01.cmd To load into flash
    V2_1 (2015.01) direct load nfm_hrptdecgen_2015_01.bit impact_fpga_2015_01.cmd To load into FPGA directly, needs to be done each time after power-up (flash content not changed)

    Bitfiles including METOP and Fengyun decoders.

    This load contains:
    VersionContentBit-fileCommand fileComment
    V0_1 (2017.04) Flash load hcmMFdecgen_flsh_01042017.mcs impact_hcmMFdecgen_flsh_01042017.cmd To load into flash
    V0_1 (2017.04) direct load hcmMFdecgen_fpga_01042017.bit impact_hcmMFdecgen_fpga_01042017.cmd To load into FPGA directly, needs to be done each time after power-up (flash content not changed)

    Extra command file for Windows

  • program2flash.bat (program to flash)
  • program2fpga.bat (program into FPGA; program lost after power-cycle)
    nfm_hrptdecgen_2015_01.xcf: pinning of the FPGA. Not needed, just for your information. (This file was used for pinning during generation of the bit-file.)

    release info:

  • V2_0: added Meteor-HRPT (N1, N2) and LRIT
    Added DiSEqC driver for 2 rotors
  • V1_0: Same as V0_7, but now officially released
  • V0_7: select VCO freq.: 10, 20, 40 MHz
  • V0_5: CHRPT generator output: bit-rate now really 1/2 of HRPT

    Older versions

    VersionContentBit-fileComment
    V1_0 (2011.03) Flash load nfm_hrptdecgen.mcs To load into flash
    direct load nfm_hrptdecgen.bit To load into FPGA directly, needs to be done each time after power-up

    pinning nfm_hrptdecgen_v10.xcf

    V0_7 (2011.03) direct load nfm_hrptdecgen_v07.bit To load into FPGA directly, needs to be done each time after power-up
    Flash load nfm_hrptdecgen_v07.mcs To load into flash
    V0_5 (2011.02) direct load nfm_hrptdecgen_v05.bit To load into FPGA directly, needs to be done each time after power-up
    Flash load nfm_hrptdecgen_v05.mcs To load into flash
    pinning nfm_hrptdecgen_v05.xcf



    Capture software

    See wsat for Windows
    Or wsat for Linux

    Information on using ISE/IMPACT

    More detailed information about how to synthesize vhdl and to make a bit-file can be found here: ISE (including Impact) information

    Received pictures

    The decoder is already build several times. For some example results see: received HRPT pictures

    Extra outputs.

    To control receiver and antenna rotors several outputs are available: