Hardware

Weersatellieten

New generation decoder

Content

To download section
Hardware
Jumper settings
Display
Signals on connectors
Programming
FPGA loads
FAQ

Introduction.

This page describes a new decoder for HRPT and derived formats. It is also suitable for future developments.

Features:

Decoders: switchable from software ('wsat') or 'real' swicthes
- PSK: HRPT, CHRPT and Meteor-HRPT
- QPSK: METOP, Fengyun-3A-C
decoder and generator for each type available at the same time
Bit integrator for noise canceller
Registermap for settings and monitoring via software
USB interface

Free software is available for capturing and some simple processing, both for Linux and Windows.

Stored data format is supported by HRPTReader.

Important notes

This decoder is not available fully assembled. You need to build it yourself.
There is currently no PCB available. But with a exp. board it's easy to do; there are just a few components to connect to each other. (No SMD to solder.)
The hardware needs to be programmed. For this you need to install special software on your PC, and a program cable. This software is free. You can choose a program cable for a parallel port or one for USB. Unfortunately the last one is very (far too?) expensive. Cable and software are just needed one time (and to load a new decoder version, if desired).

Hardware.

The hardware contains 3 main parts (see photo)

A module containing an FPGA (middle, this module is available fully assembled)
A VCO, using a few standard components (right)
FTD245 based USB interface (left); this module is available fully assembled

The 3-digit display at the bottom is optional. It shows the state of the decoder:

decoder type and synchronisation state (left)
VCO lock indication or signal quality (middle)
data buffer state (right)

Most important monitor info is also available on pins, where it can be used to drive LED's.

Note: The (green) jumper just above the dip-switches sets the needed VCO frequency to 21.2 MHz. Without this jumper 10.6 MHz is needed. Preferred (and for newest firmware) 21.2 MHz is needed!

List of components

GODIL50_XC3S500E. (including female connectors)
- GODIL manual including module schematics, pinning etc.
USB-module based on FT245: e.g.
VCO: 21.292 MHz (or 10.646 MHz):
- 74HC04
- BB809 varicap
- ...
Indications: e.g.:
- 3-digit display
- duo-LED for synchronisation state
other: e.g.:
- male double pin array (2x25) connectors for GODIL module (2 needed)
- male double pin array (2x8) connector for jumpers
5V power supply; instead of the 7805 a switched regulator is recommended:
Type: TSR 1-2450 This type doesn't need any cooling.
A 7805 needs a (big) heat spreader; the decoder needs about 300mA.

To program the FPGA a download cable is needed:

GOPLCP GOP JTAG adaptor TE0259-00 (or USB equivalent)

Schematic

GODIL has following power-pins:

GND: A1, A3, .... A25, B1, B3, ... B25
PWR: C2, C4, .... C24, D2, D4, ... D24

All power-pins are connected to each other on the GODIL module, all GND-pins are connected to each other. Normally there is no need to connect each and every pin. I think if you take the ones at the corners that's enough:

GND: A1, A25, B1, B25
PWR: C2, C24, D2, D24

For C and L around VCO several values can be used: For 10.6 MHz:

L=10 uH / C=39 pF (as in schematic)
L=15 uH / C=22 pf

For 21.2 MHz (preferred!)

L=3.3 uH / C=39 pF

Note about USB modules: This is FTD245 based. Tested are:

USBMOD4 (big square USB connector); module needs following extra connections:
- connect pin 9 (EP) to pin 10 (RSTO)
- connect pin 12 (VIO) to pin 13 (VCC)
FT245_breakout_v1 of Sparcfun (mini-USB)

Jumpers

NOTE: Inserting a jumper means: Set to 0!

x : jumper set

- : jumper not set

* : don't care

1 : logical '1', +5 V

0 : logical '0', 0 V

Choice decoder/generator type.

There are currently 3 decoder/generator types implemented; HRPT, CHRPT and MHRPT.
Two more are under beta / under construction: LRIT MSG/GOES and FY3.
The type can be set in 2 ways: by software or using jumpers.
Next table shows jumper setting (left half) and logic value (right half).

GODIL Pin	C25	A24	C23	A22	C25	A24	C23	A22	comment
Type	J1	J2	J3	J4	val	val	val	val
HRPT	x	x	x	x	0	0	0	0
CHRPT	-	x	x	x	1	0	0	0	not active
MHRPT1	x	-	x	x	0	1	0	0	not active
MHRPT2	-	-	x	x	1	1	0	0
METOP	x	x	-	x	0	0	1	0
FY3A,B	x	-	-	x	0	1	1	0
FY3C	-	x	-	x	1	0	1	0
IQ record	-	-	-	x	1	1	1	0
set by SW	*	*	*	-	*	*	*	1

VCO

You can choose between 3 different VCO frequencies. A higher frequency may give better results with integrator On.
Recommended (mandatory for newest (2017+) firmware loads): 21.292 MHz. (Note: You need to adapt L and C too for a different frequency.)

Pin	C17	A16	C17	A16
Freq MHz	J9	J10	val	val	Note
10.646 MHz	x	x	0	0	don't use for 2017+ firmare!
21.292 MHz	-	x	1	0	Use this for any firmare
42.584 MHz	x	-	0	1	don't use for 2017+ firmare!
10.646 MHz	-	-	1	1	don't use for 2017+ firmare!

Other settings.

function	Pin	jumper	set	val
enable integrator	C21	J5	-	1
disable integrator	C21	J5	x	0
invert input	A20	J6	x	0
normal input	A20	J6	-	1
middle display: quality input sig	C19	J7	x	0
middle display: lock state PLL	C19	J7	-	1

If no jumpers are set then all inputs are '1', so:

decoder type set by software
integrator on
data input not inverted
middle display shows lock state
VCO freq. should be 10.646 MHz (NOT for newest firmware!)

Extra monitor points

function	pin	comment
data clock	B24	These are EXOR-ed to phd
VCO clock	B22	These are EXOR-ed to phd
datachange eyecenter	B20	pulse width=1 VCO clockcycle
out-sync	D25	lockindication 2-colour-LED
in-sync	D23	lockindication 2-colour-LED
1=VCO too high	D21	VCO lock indication
1=VCO too low	D19	VCO lock indication
1=buffer overflow	D11

Signals on ABCD connectors

K4: right con	GODIL con	FPGA con	name	left con/dipsw	GODIL con	FPGA con	name
1	D1	P91	Generator out (I)		C1	P26	usb_data[0]
2	B2	P12	Generator out (Q)		A2	P15	usb_data[1]
3	D3	P11	decoder in (I)		C3	P16	usb_data[2]
4	B4	P10	decoder in (Q)		A4	P95	usb_data[3]
5	D5	P9	scl		C5	P18	usb_data[4]
6	B6	P90	diseqc_do[0]		A6	P17	usb_data[5]
7	D7	P5	sda		C7	P94	usb_data[6]
8	B8	P4	diseqc_do[1]		A8	P22	usb_data[7]
9	D9	P2	TX RS232		C9	P23	usb_rd
10	B10	P3	-		A10	P33	usb_wr
11	D11	P98	ovf		C11	P32	usb_txe
12	B12	P92	-		A12	P34	usb_rxf
13	D13	P88	clkb: VCO		C13	P38	-
14	B14	P85	sd_sample[0]		A14	P40	-
15	D15	P79	phd		C15	P41	-
16	B16	P78	sd_sample[1]		A16	P36	sel_vco[1]
17	D17	P83	clka: VCO		C17	P35	sel_vco[0]
18	B18	P84	-	D8	A18	P53	sel_clk
19	D19	P86	ool[0]	D7	C19	P54	dispmode
20	B20	P71	errpls	D6	A20	P57	dinv_not
21	D21	P70	ool[1]	D5	C21	P58	ena_bitintegr
22	B22	P68	ckvco	D4	A22	P60	dectype sw/manual
23	D23	P67	rg_syncled[0]	D3	C23	P61	dectype[2]
24	B24	P66	ckdat	D2	A24	P62	dectype[1]
25	D25	P65	rg_syncled[1]	D1	C25	P63	dectype[0]

Signals on display connector

GODIL con	FPGA con	name
?	sclk	P44
?	ser	P50
?	rclk	P27

Not on any connector

FPGA con	name
clkgen	P89
rled	P43
gled	P25

Programming the FPGA.

You need the already mentioned program cable and Impact software, free to download from the Xilinx web-page.

Download and install Impact software.

There are versions for Linux and Windows. Easiest is to download Impact from an older version of ISE. Go to:

Xilinx download web-site

Choose ISE Design Tools

Choose Archive (left list)

Choose 12.2

Scroll down to chapter 'Lab Tools'

Select 'All Platforms'.
Now you need to log in, or first make an account. If you have done that, you can download:
Xilinx_LabTools_12.2_.63c.1.1.tar

In Archive tool, which should pop-up now, select xsetup (Linux) of xsetup.exe (Windows)

(To continue)

After downloading and installing you should now have a tool called impact(.exe), located at: (location may differ)

Linux: /opt/Xilinx/12.2/ISE_DS/ISE/bin/lin/impact
Windows: C:\Program Files\Xilinx\12.4\ISE_DS\ISE\bin\nt

Program the FPGA using Impact.

There are 2 methods:

Use the gui
Use the command file, and a command shell

Although it is probably not what you are used to, using the command shell and command file is by far much easier than using the gui!

Instead of programming the flash you can also program directly into the FPGA. The flash is then not changed; after a power-cycle the original program in flash is loaded. In this way it possible to try a new program before "definitely" load it into flash.

Bit files and command files are available here.

Windows:

Download the bit-file (.mcs), the Impact command file (impact_flsh....cmd) and program2flsh.bat. Put them into the same directory e.g. just in C:\).
(If you want to program into fpga download the .bit file and command file 'impact_fpga....cmd', and use program2fpga.bat instead.)
(Note: For future versions only the mcs file needs to be downloaded. The .cmd and .bat file may be reused.)
Adapt program2flash.bat to your situation. Only the line starting with SET needs to be checked; this should be the path to where the impact program was installed.
Open a command shell.
Go to the place where you did put the bit/cmd/bat files:
cd c:\.
Connect decoder to the PC using the program cable, and power-up the decoder.
In the command shell start the .bat file by typing:
program2flash
Check the output in the command shell for error messages.
Programming should take about 15 seconds.

Linux:

The same mcs and cmd may be used. Command: (adapt command filename if needed)

impact -batch impact_flsh.cmd Or:

impact -batch impact_fpga.cmd

FPGA loader

This loader enables a simple selection and loading of firmware for the decoder. The firmware loader contains FPGA firmware for several releases of the HRPT etc. decoder. Loading the firmware needs following steps:

Choose temporary or semi-permanent load (fpga or flash resp.)
Choose release to load
Extract the choosen version from the loader
This will create a bit-file and command file. You may use that to load the firmware 'manually', or continue with the loader:
Click on Program, this will load the firmware into the FPGA.

For Linux, if you have a search path to 'impact' (the actual Xilinx loader) then this should just work.

For Windows, if no search path is defined to 'impact', an option can be added to define full path to the impact tool. This needs to be defined in the startup-icon, at 'property', e.g.:
ld_fpga C:\Xilinx\labtools\ISE\impact.exe

This load contains:

hrpt decoder and generator (code 0)
chrpt decoder and generator (code 1)
meteor mn1 decoder and generator (code 2)
meteor mn2 decoder and generator (code 3)
metop decoder and generator (generator does NOT generate valid formatted metop-files) (code 4)
fengyun3 decoder and generator (generator does NOT generate valid formatted fengyun3-files) (code 5)
IQ data dumper (code 7)
2x DiSEqC generators for rotors
UART output (2018.2 only), will be used to send info to tuner for frequency selection

Differences between versions:

Load version 01 uses simple dividers from the input clock/VCO. This needs some trimming of the VCO when switching from one satellite type to the other.
Load version 05 uses DCM's (input clock multipliers) to create more accurate input clocks per sat-type. Just accurate enough that trimming isn't needed. But temperature differences may cause need of trimming.
Load version 07 uses DCM's in combination with fractional dividers. This creates very accurate dividing of the input clock; a VCXO is possible. Big advantage of a VCXO is that no trimming is needed

Some possible advantages/disadvantages:

Version 01: straight design concerning clock generation, but relative big aberation of needed VCO clock between satellite types
Version 05: DCM's may be a bit sensitive to input jitter. In practice, during 1 year of usage, we don't see any problems.
Version 07: because of the fractional dividers there is a bit of inherent jitter on the internally generated base clock, even if the input clock is stable. So far we haven't seen problems. Very big advantage of a VCXO is that no trimming is needed at all
Note that the bitrate of the generators from versions 01 and 05 are by far not accurate enough to feed a decoder using a VCXO!

Versions Date Content clock loader Linux loader Windows
01 2017.8 decoders, generators, DiSEqC (needs trimming of vco between sat-types) VCO ~ 21.29 MHz ldfpga.tgz setup_ldfpga.exe

05 2017.8 decoders, generators, DiSEqC; more accurate deriving base clock VCO 21.00 MHz
07 2018.2 decoders, generators, DiSEqC; very accurate deriving base clock VCO / VCXO 20.000000, 40.000000, 80.000000 MHz
08 2018.8 better metop/fengyun generator (gives test pictures)
higher display update rate VCO / VCXO 20.000000, 40.000000, 80.000000 MHz
09 2019.3 Added NOAA20 decoder/generator
(generator currently generates metop@noaa20 rate) VCO / VCXO 20.000000, 40.000000, 80.000000 MHz coming, test fase

Versions	Date	Content	clock	loader Linux	loader Windows
01	2017.8	decoders, generators, DiSEqC (needs trimming of vco between sat-types)	VCO ~ 21.29 MHz	ldfpga.tgz	setup_ldfpga.exe
05	2017.8	decoders, generators, DiSEqC; more accurate deriving base clock	VCO 21.00 MHz
07	2018.2	decoders, generators, DiSEqC; very accurate deriving base clock	VCO / VCXO 20.000000, 40.000000, 80.000000 MHz
08	2018.8	better metop/fengyun generator (gives test pictures) higher display update rate	VCO / VCXO 20.000000, 40.000000, 80.000000 MHz
09	2019.3	Added NOAA20 decoder/generator (generator currently generates metop@noaa20 rate)	VCO / VCXO 20.000000, 40.000000, 80.000000 MHz	coming, test fase

Older releases

Bitfiles for XC500 on GODIL 50 board. Contains:

Decoders for HRPT, CHRPT, MHRPT (N1 and N2), LRIT
Generators for HRPT, CHRPT, MHRPT (N1 and N2), LRIT
DiSEqC for 2 rotors

Version	Content	Bit-file	Command file	Comment
V2_1 (2015.01)	Flash load	nfm_hrptdecgen_2015_01.mcs	impact_flsh_2015_01.cmd	To load into flash
V2_1 (2015.01)	direct load	nfm_hrptdecgen_2015_01.bit	impact_fpga_2015_01.cmd	To load into FPGA directly, needs to be done each time after power-up (flash content not changed)

Bitfiles including METOP and Fengyun decoders.

This load contains:

hrpt decoder and generator (code 0)
chrpt decoder and generator (code 1)
meteor mn1 decoder and generator (code 2)
meteor mn2 decoder and generator (code 3)
metop decoder and generator (generator does NOT generate valid formatted metop-files) (code 4)
fengyun3 decoder and generator (generator does NOT generate valid formatted fengyun3-files) (code 5)
IQ data dumper (code 7)
2x DiSEqC generators for rotors

Version	Content	Bit-file	Command file	Comment
V0_1 (2017.04)	Flash load	hcmMFdecgen_flsh_01042017.mcs	impact_hcmMFdecgen_flsh_01042017.cmd	To load into flash
V0_1 (2017.04)	direct load	hcmMFdecgen_fpga_01042017.bit	impact_hcmMFdecgen_fpga_01042017.cmd	To load into FPGA directly, needs to be done each time after power-up (flash content not changed)

Extra command file for Windows

program2flash.bat (program to flash)

program2fpga.bat (program into FPGA; program lost after power-cycle)

nfm_hrptdecgen_2015_01.xcf: pinning of the FPGA. Not needed, just for your information. (This file was used for pinning during generation of the bit-file.)

release info:

V0_1 2017.04: added METOP, Fengyun; use 20 MHz for VCO!

V2_0: added Meteor-HRPT (N1, N2) and LRIT
Added DiSEqC driver for 2 rotors

V1_0: Same as V0_7, but now officially released

V0_7: select VCO freq.: 10, 20, 40 MHz

V0_5: CHRPT generator output: bit-rate now really 1/2 of HRPT

Older versions

Version	Content	Bit-file	Comment
V1_0 (2011.03)	Flash load	nfm_hrptdecgen.mcs	To load into flash
V1_0 (2011.03)	direct load	nfm_hrptdecgen.bit	To load into FPGA directly, needs to be done each time after power-up
	pinning	nfm_hrptdecgen_v10.xcf
V0_7 (2011.03)	direct load	nfm_hrptdecgen_v07.bit	To load into FPGA directly, needs to be done each time after power-up
V0_7 (2011.03)	Flash load	nfm_hrptdecgen_v07.mcs	To load into flash
V0_5 (2011.02)	direct load	nfm_hrptdecgen_v05.bit	To load into FPGA directly, needs to be done each time after power-up
	Flash load	nfm_hrptdecgen_v05.mcs	To load into flash
	pinning	nfm_hrptdecgen_v05.xcf

Capture software

See wsat for Windows
Or wsat for Linux

Information on using ISE/IMPACT

More detailed information about how to synthesize vhdl and to make a bit-file can be found here: ISE (including Impact) information

Received pictures

The decoder is already build several times. For some example results see: received HRPT pictures

Extra outputs.

To control receiver and antenna rotors several outputs are available:

I2C (for receiver control; not tested yet)
- scl=P2
- sda=P5
RS232 (19.2kb/s):
- tx=P9
DiSEqC
To handle 2 rotors having just 1 fixed address 2 DiSEqC outputs are available:
- diseqc_do[0]=P90
- diseqc_do[1]=P4