It is ment to check that the PLL gets locked and the decoder gets in-sync.
The output is a split-phase signal. The data-content is a repeating frame-sync pattern: 60 sync-bits repeating every 63 cycles.
After 1109 bits the sequence starts again; 100 sequences makes exactly 1 HRPT-frame.
The picture will show as a more or less random pattern of vertical bars with different grey values.
For HRPT the 4060 should oscillate at about 21.28 MHz.
This gives 1330 kHz at pin 7, which is needed to generate the split-phase signal (2x HRPT bit-frequency=665 kHz).
NOTE: Coil should be 3 uH!
For PDUS you need a 166.66x2=333.33 kHz output of the 4060. You can:
I have never tested the HRPT-pattern generation, but PDUS works. For PDUS you don't need the 74HCT153 and the last 74HCT163.
For this pattern you need a 333.33 kHz output of the 4060.
Connect PDUS_RES with RESET and use PDUS_OUT.
Download EPROM content for PDUS pattern generation: pduspat.bin (5824 bytes)
(explanation file size: 1 frame has 364 bytes, each bit of a byte needs 1 EPROM-byte, so 364x8 = 2912; for split-phase: x2 = 5824 bytes).
Schema HRPT generator