Hardware description.

Schematic and PCB of the decoder/generator.

Schema decoder PDFPrint PDF


The left half in the schematic is the actual decoder/generator; the right half is the data buffer.
The two big square boxes (IC1, IC4) are so-called FPGA's. The EPROM (IC2) contains the program to load into the 2 FPGA's. This happens automatic as soon as the power is switched on. 256k is enough to contain 4 programs (decoder/generator for HRPT/PDUS).
Note that just one of these programs is active at a time. So, decoder and generator are not available at the same time!


At the left-bottom you can see the decoder's data input and the generator's data output.

Six optional channel switches may be connected to CON1 (between CON1 and +5V), to select one or more of the 5 HRPT-channels and/or the remaining info present in the HRPT-frame. Normally, you don't need these switches because selection is done by means of the computer, via the parallel port. If you want to use the switches, then remove D3-D8 and remove the connection on CON2 between pin 1 and 2. (Note that the correct info which channels are selected is saved in the file! Selecting different channels via hardware and software could give corrupt files!)

Selecting channels at the hardware instead of by means of software has the advantage that the data rate to the computer is lower, so a slow computer can be used to record e.g. 1 channel.
The data selector is not suitable for Seawifs; in this case all channels have to be recorded.
In PDUS mode channel selection is not possible.

The 2 switches and jumper at the top select a segment of the EPROM. For the current EPROM the meaning is:

HRPT decoderopenopenopen
HRPT generatoropenopenclosed
HRI decoderclosedopenopen
HRI generatorclosedopenclosed
CHRPT decoderclosedclosedopen
CHRPT generatorclosedclosedclosed
(HRPT decoder copy)openclosedopen
(HRPT generator copy)openclosedclosed

Just selecting another segment of the EPROM is not sufficient; the FPGA has to load the new selected content. This is done by means of the components connected to pin 55. It works only for switching between HRPT/PDUS/decoder/generator. If jumper SX is closed or opened the power has to be disconnected for a short while, to force a reload. (You can also connect pin 55 to GND for a short while.)

At the bottom of IC1 there are 6 LEDS, showing which channels are selected.

The components around inductor L1 determine the central frequency of the VCO of the PLL; R3, R4 and C3 act as loop filter. Pin 50 is the output of the phase comparator (EXOR type).

More to the right a LED 'err' shows if there are data errors and/or PLL lock problems. The dual-LED shows if the decoder is in-sync:

On connector block CON2 pin 1 has to be connected to pin 2; the remanining pins should be unconnected. See the data sheets for description of the pins connceted to it.

On connector block CON7 you can add LEDs for separate PLL (1) and data (2) error indication, if you like. LED ERR on CON 6 is a ORed version of these 2 pins.


Data has to be buffered because the computer can not read data continuously (interrupts, data has to be saved on disk etc.). An elastic store collects the continuous data stream from the decoder; the computer can read the data from this buffer in bursts.

IC5 is a 256kx4 bits dynamic RAM; IC4 (the second FPGA) acts as RAM controller. The buffer is able to handle 64k words of 12 bits each.

The frequency of the XTAL is not very important; a suitable value is 4.43 MHz (TV PAL XTAL); but any value between 1 and 5 MHz should work.

At the right-top the connection with the parallel port of the PC is shown. Note that a part is used bidirectional (input: selection of channels; output: 6 of the data bits). Best is to use a parallel port of type EPP, but an old fashioned type with open-collector output is also OK.

The 12 data bits going to the PC are:

CON9 and CON10 are for future use; you can ignore them for now.

Using without buffer.

If buffering is done in another way (e.g. by means of DMA, in the PC) you can just remove the right part. The connections going to pins 14-20 and 23-28 of IC4 are the 13 data/control lines you need to handle. Also, you need to do channel selections, these are the lines to CON1 at the far left.

See conflict warning!