The decoder needs just one adjustment. Probably everything will work directly, but in case of troubles here is a step-by-step put-into-use description.
The receiver of Sam Elsdon has inverted output. By connecting pin 9 and 10 of CON2 (forcing pin 30 of IC1 low) the HRPT-input will be inverted, compensating the Eldson-receiver inversion.
Note that in that case, if you use the HRPT-generator as described here, this generator's output has to be inverted too!
Note: Make sure that you insert the FPGAs the right way into their sockets!!!
Test the decoder/generator part.
For this part you don't need IC4 and IC5 (the elastic buffer part). (If you did already add them: No problem.)
Test decoder solo.
- Don't connect the decoder to receiver or PC.
- Connect power.
- The FPGAs need a fraction of a second to read data from the EPROM.
During this time the address space of the EPROM will be scanned one time.
Input LDC (pin 36, "Low During Configuration") should go high after
this time, disabling the EPROM (pin 20+22 of the EPROM).
If LDC stays 'low' probably a connection between EPROM and FPGA is broken.
- The dual-LED should show 'red' (out of sync)
- FPGA's should not warm up (not even a bit).
- Connect 5V to pin 17 of the parallel port (decoder still not
connected to PC!) Now the hardware switches from decoder to generator.
- The dual-LED should now flash between red and green (about every second)
- If channel LEDs are on, then connect pin 16 to GND for a moment.
All channel LEDs should switch off.
- Remove 5V from pin 17. ==> hardware switches back to decoder.
- Trim C2.
- Add a square wave of about 100kHz to the input (TTL level).
- Measure frequency on pin 76 of decoder-FPGA. (Test pin SCO on new PCBs.)
This should be 665.4 kHz.
Trim C2 until the frequency is OK. The VCO frequency is now 10.6464 MHz.
If needed change L1 and/or C2.
- NOTE: The PLL may NOT lock during this procedure! Pin 63 is the
lock detector output; 0V=in-lock, +5V=out-lock. Better is to change the input frequency a bit; the frequency on pin 76 should not change.
If the PLL locks (on a harmonic component), repeat this procedure with a different input frequency.
- Check PLL.
- Change frequency at input to 665.4 kHz. The PLL should now lock
(pin 63 ==> 0V). (This simulates a split-phase signal of all-zeros or all-ones.)
- Connect separate HRPT generator to input.
- Sync-LED should switch from red to green (in-sync).
Test connection between decoder and PC.
If the decoder FPGA works as described above the second FPGA may now be added.
- Make sure that the parallel port is in EPP mode.
If the parallel port is an old one with open-collector outputs this
is also OK.
- Cable between PC and decoder should not be too long (1 meter is fine).
A bad and/or too long cable could show crosstalk between the wires. This can cause spickles at certain positions of the picture, or spontaneous on/off switching of channels.
- Connect PC to decoder and switch on decoder.
The alarm LED should go on after a few seconds
(buffer overflow because PC doesn't read data).
(Time depends on how many channels are selected "by accident"
- Start software. Make sure that you select the right port.
- Select Edit -> Preferences to check/change the port.
- Channel LEDs should go off if they were on.
- Select Record in menu.
- Try to select channels by clicking on H/1...5 in the record menu.
- Select generator (click on Gen).
- Try again to select channels by clicking on H/1...5.
- If channel LEDs are more or less randomly switching on and off
probably the channel select line in the parallel cable gets noise from
surrounding wires (crosstalk). This is pin 16 of the parallel port.
The new PCB has a RC filter (R14/C11); you can try to make C11 a bit
larger (e.g. 10nf).
For the old PCB you have to add this filter (a resistor of about
100 ohm between pin 16 and the PCB, and a capacitor somewhere between
1 .. 10 nf between pin 16 and GND).
This should be enough to filter away very narrow spikes.
These currents are measured with all components (including LEDs) mounted, and PC connected. If the PC is disconnected current will be a few mA lower.
If 2 numbers are given the first is with all channels off, second all
|HRPT ||CHRPT ||HRI
If pin 14 is low, and at the same time the parallel port is in output mode, a dangerous conflict situation exists resulting in high currents!
There are a few PC types which come into this situation during boot. After boot the situation may not dissappear because of latchup.
Eventually, this can destroy your decoder and/or parallel port!
Watch the power-consumption of your decoder. If it is much higher than 500mA (during and after boot) while this is not the case if you dont connect the decoder to the PC, add resistors of 22 ohm in series with pin 2-9 of the parallel port. This is not an ideal situation because the resistors will make the wires more sensitive to crosstalk between wires. An other possibility is to add some logic to pin 14 which makes this pin high during boot time (e.g. 1 minute).
If everything is OK you can try to make your first recording.
Note that you can read pictures to the screen without saving it into a file.
Click on Save in file; becomes Don't save.
In this way you can play without making huge files.
Read the manual for more details.
- Switch to generator mode.
- Select channel 1.
- Click on Start.
- Recording starts; at the same time you will get a picture on screen.
See Test pictures.
- After a few seconds the alarm LED of the buffer should go off.
You can also show the state of all parallel port pins by clicking on Test. Note that the alarm LED will go on because updating the screen is relatively very slow (slower than the data rate).