Extracting.

Extracting bitstream from received signal.

The conversion of the demodulated signal (the split-phase signal) into a serial bit stream needs special attention. In the current decoder this is done as follows:

The split-phase-signal is converted into a TTL-level signal (done in the receiver, by means of a simple comparator).

A PLL locks on this signal. A counter is used to generate 2 samples for each bit:

split-phase  ____----____----____--------____----________----
             <------><------><------><------><------><------>
              (1 bit)    0       0       1       1       0
sample       ___|___|___|___|___|___|___|___|___|___|___|___|_
                a   b   c   d   e   f   g   h   i   j   k   l

Every other sample is taken to get the actual bits. By comparing 2 samples in a row it is possible to determine which of each pair has to be taken: the actual taken sample and the next one have to be always '01' or '10'.
In the picture above, samples a,c,e,g,i,k have to be taken. Sample f, for example, is followed by sample g, both being '1', so sample 'f' is the wrong one.
At samples a-e it is impossible to see if these represent '1' or '0'. Only if the actual transmitted bit changes between '0' and '1' this is possible. So, if by accident samples b/d/f are taken, at sample 'f' an error will be detected; from there bits g/i/k etc. will be taken.

This method works fine for strong signals, like HRPT. However, with PDUS the received signal is too weak to get a usable picture.
A few circuits have been tried out to deterimine how to get usable PDUS pictures, using antennas of max. 1.5 m:

By means of an analog integrator, working at the signal before clamping it to TTL level.
By means of a digital integrator, working at the TTL-level signal (invented by Harry v. Deursen)

Both methods give a considerable enhancement. The second one is suitable to build into the FPGA, which minimizes the amount of extra needed hardware.

Results new bit-extractor.

The conversion analog-to-TTL has been improved by means of a LPF filter in the analog part. This simple filter gives already much better results!

The digital integrator has been added to the PDUS decoder. Result: Again a big improvement!

Simulations.

Next pictures show simulation results of the analog and digital integrator.

A=noise free split-phase signal
B=noisy split-phase signal
C=integration result
D=sample moment

Result without integrator.
Low noise	High noise

Result with analog integrator (in front of decoder)
High noise	Very high noise, half period integration	Very high noise, full period integration

Result with digital integrator (in FPGA).
No noise	Very high noise

Conclusions

For HRPT, the receiver/decoder as-is is good enough to get usable pictures. However, a low pass filter before going to TTL level is easy to add, and will probably give a considerable improvement (usable signal at low elevations and/or smaller antenna).

For PDUS at least the bit-integrator is a 'MUST' to get usable pictures.