FPGA BITFILE.
These are the EPROM bit-files for the HRPT/PDUS and HRPT/CHRPT decoder/generator
Note: The programs should be loaded in the mentioned segments.
If another partition is needed then D2 on the PCB should be removed. This disables the automatic reload after selecting another segment. In this case the power should be disconnected for a short while, after choosing another segment.
NOTE: The only differences between the 3 files are the combinations of decoders/generators. The decoders/generators of a certain type (HRPT, CHRPT, HRI) are the same in all 3 files.
File 1: HRPT and PDUS (version 7b). Load from address 0000 or 8000 (hex).
Needed space: 32kB. Minimal EPROM: 27(C)256 or equivalent.
| Address space (hex)
| Content
|
| Segment 1
| 0000 - 1FFF
| HRPT decoder
|
| Segment 2
| 2000 - 3FFF
| HRPT generator
|
| Segment 3
| 4000 - 5FFF
| PDUS decoder
|
| Segment 4
| 6000 - 7FFF
| PDUS generator
|
Download hdgpdg7b.bin (32k) (Binairy format)
Download hdgpdg7b.mcs (90k) (Intel HEX format)
File 2: HRPT and CHRPT (version 1). Load from address 8000 or 0000 (hex).
Needed space: 32kB. Minimal EPROM: 27(C)256 or equivalent.
Programs:
| Address space (hex)
| Content
|
| Segment 1
| 0000 - 1FFF
| HRPT decoder
|
| Segment 2
| 2000 - 3FFF
| HRPT generator
|
| Segment 3
| 4000 - 5FFF
| CHRPT decoder
|
| Segment 4
| 6000 - 7FFF
| CHRPT generator
|
Download hdgcdg1.bin (32k) (Binairy format)
Download hdgcdg1.mcs (90k) (Intel HEX format)
File 3: HRPT, PDUS en CHRPT (version 1). Load from address 0000 (hex).
Needed space: 64kB. Minimal EPROM: 27(C)512 or equivalent.
This is a combination of file 1 and file 2.
Programs:
| Address space (hex)
| Content
| SX/SD/SM
|
| Segment 1
| 0000 - 1FFF
| HRPT decoder
| off/off/off
|
| Segment 2
| 2000 - 3FFF
| HRPT generator
| off/off/on
|
| Segment 3
| 4000 - 5FFF
| PDUS decoder
| off/on/off
|
| Segment 4
| 6000 - 7FFF
| PDUS generator
| off/on/on
|
| Segment 5
| 8000 - 9FFF
| HRPT decoder
| on/off/off
|
| Segment 6
| A000 - BFFF
| HRPT generator
| on/off/on
|
| Segment 7
| C000 - DFFF
| CHRPT decoder
| on/on/off
|
| Segment 8
| E000 - FFFF
| CHRPT generator
| on/on/on
|
Note:
- SM is done via (pin 17 parallelport). No switch needed.
- Switch SD is needed; FPGA reloads itself.
- Switch SX is needed; FPGA does NOT reload itself.
Switching between lower and upper half needs a short power-break, to force a re-load. The automatic reload doesn't work if just A15 is changed.
(As an alternative you can toggle SD after switching SX.)
Download hphcdg1.bin (64k) (Binairy format)
Download hphcdg1.mcs (180k) (Intel HEX format)
Information version 7b.
Difference with version 7a:
Pin 42 was output in HRPT-mode; this can give conflicts on the new PCB.
The pin is now not active in HRPT mode.
Functional no difference with 7a.
IMPORTANT for Intel Hex format:
The original Intel-HEX files did contain the following first line:
:020000020000FC
The red number shows that this is a so-called paragraph record (or: Extended segment address record).
Not all PROM-programmers seem to interpret this correctly.
To prevent problems I did remove the first line (as far as I know this line is not mandatory if the extended address is zero).
TEST VERSION
This is a testversion of the HRPT-decoder. It contains a digital integrator and bit-slip processing, just like the HRI decoder. HRPT-generator and HRI-decoder/generator are also added, but these are the same as the standard version.
Description.
It seems that the integrator does work (less speckles). Unfortunately, for some reason the decoder gets out-of-sync many times, resulting in errored lines. Therefore, overall, this decoder is worse than the 'standard' version.
Please let me know your results if you did try this decoder!!
TEST VERSION, contains all decoders
- HRPT decoder with integrator
- HRPT generator
- HRI decoder with integrator
- HRI generator
- HRPT decoder without integrator (same as the one in 'File 3')
- HRPT generator
- CHRPT decoder with integrator
- CHRPT generator