PCB decoder.

Content:

Pinning
Interface

Pinning HRPT/PDUS decoder/generator FPGA.

Note 1:

EPROM connections are not mentioned.
Input PU means: Input with pull-up. If not used, don't connect.
Not used inputs without pullup have to be connected to GND or VDD.
During configuration some pins have a different meaning. In functional mode these pins are only used for outputs to prevent conflicts during configuration.

Note 2:

HRPT decoder also works for SeaWifs (if not encrypted...). However, channel selection does NOT work properly! In this case ALL channels have to be selected (so all 8 channels will be recorded).

Note 3:

+ means: Used in this mode.
- means: Not used in this mode.
* means: Different meaning in this mode; see other definition.

Data related pins.

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
35	SDI	Input	data input (split-phase)	+	-	+
37	SDO	Output	data output (split-phase)	-	+	-
30	DINV	Input PU	invert SDI/SDO; 1=normal, 0=invert	+	+	+
5	PDO1	Output	Data out; MSB	+	+	+
4	PDO2	Output	Data out	+	+	+
3	PDO3	Output	Data out	+	+	+
84	PDO4	Output	Data out	+	+	+
83	PDO5	Output	Data out	+	+	+
82	PDO6	Output	Data out	+	+	+
81	PDO7	Output	Data out	+	+	+
80	PDO8	Output	Data out	+	+	+
79	PDO9	Output	Data out	+	+	-
78	PDO10	Output	Data out; LSB	+	+	-
11	SDT	Output	Strobe output	+	+	+
2	STRTFRM	Output	Start frame	+	+	-
42	FRSTWRD	Output	First word	+???	+???	*
65	STRTDAT	Output	first word of frame at PDO	+	+	+

Relation PDO and SDT:

PDO	====X===============X=======
SDT	____--------________--------

Note:

If channel 'H(eader)' is selected (record also all non-picture data) then STRTDAT='1' during first word in frame.
If 'H(eader)' is NOT selected then STRTDAT='1' during first word(s) of selected channels (words 751-755 of frame)

Channel selection.

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
13	SEL1	Input	Select channel 1	+	+	-
14	SEL2	Input	Select channel 2	+	+	-
15	SEL3	Input	Select channel 3	+	+	-
16	SEL4	Input	Select channel 4	+	+	-
17	SEL5	Input	Select channel 5	+	+	-
18	INFO	Input	Select remaining data	+	+	-
21	ALLD	Input PU	'0'=Select all channels (=SEL1-SEL5+INFO)	+	+	-
38	SELO1	Output	'1'=channel 1 selected	+	+	*
39	SELO2	Output	'1'=channel 2 selected	+	+	*
40	SELO3	Output	'1'=channel 3 selected	+	+	*
41	SELO4	Output	'1'=channel 4 selected	+	+	*
44	SELO5	Output	'1'=channel 5 selected	+	+	*
45	INFOO	Output	'1'=channel I selected	+	+	*
23	OEN	Input PU	output enable	+	+	+
19	CSN	Input PU	chip select	+	+	-
20	WEN	Input PU	write enable (channel select)	+	+	-
24	MAN	Input PU	manual channel select	+	+	-

Status pins.

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
67	NINSYNC	Output	'0'=in-sync	+	+	+
68	NOUTSYNC	Output	'0'=out-sync	+	+	+
71	STATE2	Output	'1'=???	+	+	+
63	ERR_C	Output	'1'=PLL error	+	+	+
62	ERR_D	Output	'1'=data error	+	+	+
66	ERR	Output	ERR_C OR ERR_D	+	+	+
75	OUT_LOCK	Output	???	+	+	*
75	ERR_CI	Output	???	*	*	+
38	SAMPCNT0	Output	sample counter at decision	*	*	+
39	SAMPCNT1	Output	sample counter at decision	*	*	+
40	SAMPCNT2	Output	sample counter at decision	*	*	+
41	SAMPCNT5	Output	sample counter at decision	*	*	+
44	SAMPCNT6	Output	sample counter at decision	*	*	+
45	SAMPCNT7	Output	sample counter at decision	*	*	+

PLL/Clock pins.

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
50	PHD	Output	phase detector output	+	+	+
53	XTAL2	Input	Coil for VCO (10.6464 MHz)	+	+	+
57	XTAL1	Output	Coil for VCO (10.6464 MHz)	+	+	+

Other pins.

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
48	SPRG1	Input	xxx	+	+	+
42	SPRG1	Output	First word	*	*	+
49	SPRG2	Input	xxx	+	+	+
56	N_PRG	Output	xxx	+	+	+

Debug pins.

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
60	CKDAT	Output	clock extracted from data	+	+	+
61	CKVCO	Output	VCO output	+	+	+
59	CKW	Output	Word clock (66.54 kHz)	+	+	+
73	D_SAMP	Output	Internal sampled data	+	-	-
72	SAMP_PLS	Output	internal data sample pulse	+	-	-
70	SYNCW1	Output	sync word 1 recognized	+	*	+
69	SYNCPLS	Output	All sync words recognized	+	-	+

Remaining pins (not used (yet)).

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
26	SAMPM2	Input PU	sample moment MSB	+	-	*
27	SAMPM1	Input PU	sample moment	+	-	*
28	SAMPM0	Input PU	sample moment LSB	+	-	*
26	SEL_SYNC	Input PU	'0'=in-sync state different	*	-	+
27	SEP_CKI	Input PU	'0'=separate clock	*	-	+
28	CKI	Input PU	sep. clock	*	-	+
10	SD1	Output	'1' if channel 1 at PDO	+	+	-
9	SD2	Output	'1' if channel 2 at PDO	+	+	-
8	SD3	Output	'1' if channel 3 at PDO	+	+	-
7	SD4	Output	'1' if channel 4 at PDO	+	+	-
6	SD5	Output	'1' if channel 5 at PDO	+	+	-
76	SCO	Output	clock for serial data out	+	+	+
77	SDO	Output	serial data out	+	+	+
25	F_DEXTR	Input PU	decision data extr. '0'=decide at each bit '1'=decide if out-of-sync	+	*	-
25	PICINVOFF	Input PU	picture inversions vertical '0'=suppress	*	+	-
70	VERT_INV	Output	picture inverted	*	+	*

Special pins.

Pin	Name	Type	Comment	HRPT decoder	HRPT generator	PDUS decoder
1	GND	Power	xxx	+	+	+
43	GND	Power	xxx	+	+	+
22	VDD	Power	xxx	+	+	+
64	VDD	Power	xxx	+	+	+
31	M1	config. FPGA	GND	+	+	+
32	M0	config. FPGA	GND	+	+	+
33	M2	config. FPGA	VDD	+	+	+
36	LDC	(Output)	Low during configuration	+	+	+
34	HDC	(Output)	High during configuration	+	+	+
55	DONE-PG	Input	'0'=Reload FPGA	+	+	+
74	CCLK	Output	config. clock	+	+	+
12	PWRDWN	Input	Power-down	+	+	+
54	RESET	Input		+	+	+

Not used pins.

Pin	Comment
9
46
47
51
52
58	Only used for EPROM addressing

Pinning elastic store controller FPGA.

Note: The following signals are buffered:

PDO1-PDO10: 10 data bits
STRTDAT: '1' if first word of frame is at PDO
FRMOK: '1' if frame OK (=sync LED green,= at least 2 frames received)

Data pins.

Pin	Name	Type	Comment
15-20,23-28	DI11 ... DI0	Input PU	Data in
6-3,84-77	DO11 ... DO0	Output	Data out

RAM pins.

Pin	Name	Type	Comment
38,37,35,34	RAMD3 ... RAMD0	Bidir PU	Data IO
52-44	RAMA8 ... RAMA0	Output	Address
40	WEN	Output	write enable
41	RAS	Output	Row refresh
39	CAS	Output	Column refresh
29,30	S_RAM1,S_RAM0	Input PU	RAM size ('11'=256 words)

Control/status/clock pins.

Pin	Name	Type	Comment
68	R_CLK	Input PU	Read data
14	W_CLK	Input PU	Write data
70	READYN	Output	Data at output ready
71	ACKN	Output	-
56	ALARM	Output	Buffer overflow
58	EMPTY	Output	Buffer empty
63	OEN	Input PU	Output enable
21	OEI	Input PU	Invert OE pin
53	XTAL2	Input	XTAL oscillator (about 4 MHz)
57	XTAL1	Output	XTAL oscillator (about 4 MHz)

Pins for 3x4 and 2x6 modes. (Not used yet.)

Note: Maybe 2x6 will be used in future to inteface with USB interface.

67,65,62-59 DO_N5 ... DO_N0 Output 3 steps of 4 bits or 2 steps of 6 bits
13 R_CLK Input PU pulse to get next nibble/sextet
66 RDY_NIB Output Ready full word (third nibble or second sextet)
69 NIB_MOD Input PU '1'=3x4 bits, '0'=2x6 bits

Interface with PC.

The hardware is designed to interface with a PC using the parallel port. In the future I hope to design a USB interface.

Speed problems.

NOTE First read xtal frequency information.

Unfortunately, the speed of the parallel port is limited; a fast PC doesn't improve that. The speed is enough to transport all data of a 5 channel NOAA satellite (65k words per second). Fenyung satellites, however, needs double speed data transfer (130k words per second) if all 10 channels are selected. This is just too fast for the parallel port. The alarm LED of the buffer will light up now and then, and data will be missed (horizontal lines in picture). The easiest way to circumvent this problem is to select not more than 8 channels to record.

The Linux/Windows software wsat now has a way to record all channels. This needs a bit of extra logic: signal READYN (pin 10, see below) has to be delayed a bit more than the slowest data bit. It is still possible that this delay is too much; in that case the par. port is really too slow. For best result keep the par. port cable a short as possible.

Background.

See pictures below; signal 'readyn' should go low AFTER all data bits are settled. Normally this is done by the software by polling 'readyn' until it is low, then an extra read cycle is done to make sure that the data is stable. This extra read cycle takes longer than actually is needed. In the fast mode this extra read isn't done. Adding a bit extra delay in signal 'readyn' should result in a clean datatransfer.

What to do:

For a first try you don't need to add the extra logic. In the software:

go to the Preferences menu ('Edit->Preferences')
select 'Interface'.
activate 'Fast parport access'.
select 'Use' (for temporarly use) or 'Save' (to save selection in preferences file)

Now go to the 'Record->HRPT' window.

Select CHRPT, generator mode, enable all 10 channels and start recording. No actual save is needed; select channel 1 to show during record.
You will notice that the alarm LED won't light up, but the picture will look very noisy.
Now do a real record. If the alarm LED stays off then in principle the par. port/PC is fast enough to go on. If the LED goes on now and then (may happen 1x every 20 secs or so) then it doesn't make sense to go on; the PC/par. port is too slow. (You may try to shorten the par. port cable.)

Add the following logic:

Set the 5k R to minimum. Start recording (no save needed), enable all channels and select channel 1 to show during record. The picture will still look noisy.
Adjust the 5k R until your picture looks noise free.
Check if the alarm LED stays off (i.e., no hor. spurious lines in picture) during 1 min.
Start recording, with save on. Check if alarm LED stays off. If not, bad luck; at least one of the data lines is too slow. Maybe a shorter par. port cable helps.

In my case, with a 166 MHz Pentium without the extra logic, recording is already too slow. If I switch off saving then data capture is fast enough, but adding extra delay until there is a noise free picture makes the whole capture process too slow again.

Conclusion:

With a fast PC and a short par. port cable there is a chance that you can just capture all 10 CHRPT channels. Note that in generator mode, several channels will look fine, but especially channel 1 is very sensitive to noise. This is because channel 1 is next to channel 10 of previous line, and a lot of data bits are changing going from channel 10 to channel 1.

Recording:

DECODER		PAR. PORT	PORT PIN NUMBER	Waves	Comment
DO	==>	D, status	[9-2,12,13,15,11]	==x========	New data on output
READYN	==>	ACKN	[10]	----___----	zero: Data ready to transfer
R_CLK	<==	STROBE	[ 1]	------_----	Read data done; give new data
OEN	==>	Auto feed	[14]	___________	'0'; Outputs decoder enabled
WEN	==>	INIT	[16]	-----------	'1'; don't write to decoder
DEC0_GEN1	==>	Select	[17]	???	'0' in decoder mode, '1' in generator mode

Description:

Hardware: Data is put on output. READYN goes '0' to let PC know data is ready.
PC: Detects ACKN='0', reads data and gives strobe pulse to hardware.
Hardware: Gets strobe pulse on R_CLK; READYN goes '1' until new data is ready on output.
OEN goes '0' if recording starts and '1' at end of recording(decoder ouputs data)
WEN always '1' (don't write channel sle. to decoder)
DEC0_GEN1 '0' in decoder mode, '1' in generator mode.

Some times I measured on my parallel port:

pin 10 ---______________-----------------------------_______
                        <-------------t3------------>
          <-----t1----> 

pin 1  ----------------______-------------------------------
                       <-t2->

t1=4 us = reaction time PC: pin 10 low ==> catch data and generate strobe pulse on pin 1
t2=1.8 us dependent on speed par. port
t3 depends on data speed, so amount of channels selected. HRPT, all channels -> t3=11us (15-t1); 1 channel selected: t3=54 us (58-t1)
(Note: In both cases frame header info containing 800 words is enabled. So, 1 channel selected means 2048+800 words per 166ms; all channels selected gives 10240+800words per 166ms.)

Data pins parallel port.

Pin	Function
15	in-sync
11	start frame
9	D1 (MSB)
8	D2
7	D3
6	D4
5	D5
4	D6
3	D7
2	D8
12	D9
13	D10 (LSB)

Channel selection:

Note: For data selection by software input MAN (pin 24 of decoder-FPGA) should be forced to '0'.

DECODER
PAR. PORT PORT PIN NUMBER Waves Comment
DO ==> D [8-3] zz=======zzz Put channel selection on decoder input
OEN ==> Auto feed [14] ----------- '1'; Outputs decoder disabled
WEN ==> INIT [16] -----__---- write to decoder

DECODER		PAR. PORT	PORT PIN NUMBER	Waves	Comment
DO	==>	D	[8-3]	zz=======zzz	Put channel selection on decoder input
OEN	==>	Auto feed	[14]	-----------	'1'; Outputs decoder disabled
WEN	==>	INIT	[16]	-----__----	write to decoder

Description:

PC: Puts parport into output mode, channel selection on parport and then gives neg. pulse on WEN
Hardware: Saves channel selection.
PC: Puts parport into input mode, to be on the save side ('z'=high-impedance)
OEN always '0' (decoder ouputs disabled)

67,65,62-59	DO_N5 ... DO_N0	Output	3 steps of 4 bits or 2 steps of 6 bits
13	R_CLK	Input PU	pulse to get next nibble/sextet
66	RDY_NIB	Output	Ready full word (third nibble or second sextet)
69	NIB_MOD	Input PU	'1'=3x4 bits, '0'=2x6 bits